Verilog实现MIPS的5级流水线cpu设计（Modelsim仿真）[通俗易懂]

`define RstEnable 1'b1 `define RstDisable 1'b0 `define ENABLE 1'b1 `define DISABLE 1'b0
`define WriteEnable 1'b1 `define WriteDisable 1'b0 `define ReadEnable 1'b1 `define ReadDisable 1'b0

`define InsEnable 1'b1 `define InsDisable 1'b0 // common constant define `define ZeroWord 32'h00000000 // bus width define `define InsAddrWidth 31:0 `define InsWidth 31:0 `define InsAddrBus 31:0 `define InsDataBus 31:0 `define RegAddrBus 4:0 `define RegDataBus 31:0 `define DRegDataBus 63:0 // number of objects `define InsMemUnitNum 262143 `define InsMemUnitNumLog2 18 `define RegFilesNum 32 `define RegFilesNumLog2 5 // instructions encoding `define SPECIAL 6'b000000 `define SPECIAL2 6'b011100
`define REGIMM 6'b000001 // 0. NOP `define NOP 6'b000000 // SPECIAL `define PREF 6'b110011 //SPECIAL `define SYNC 6'b001111

// 1. LOGIC Insts
`define AND 6'b100100 // SPECIAL `define OR 6'b100101 // SPECIAL `define XOR 6'b100110 // SPECIAL `define NOR 6'b100111 // SPECIAL

`define ANDI 6'b001100 `define ORI 6'b001101 `define XORI 6'b01110 `define LUI 6'b001111

// 2. SHIFT Insts
`define SLL 6'b000000 // SPECAIL `define SRL 6'b000010 // SPECIAL `define SRA 6'b000011 // SPECIAL `define SLLV 6'b000100 //SPECIAL
`define SRLV 6'b000110 //SPECIAL `define SRAV 6'b000111 //SPECIAL // 3. MOVE Insts `define MOVN 6'b001011 // SPECIAL `define MOVZ 6'b001010 // SPECIAL
`define MFHI 6'b010000 // SPECIAL `define MFLO 6'b010010 // SPECIAL `define MTHI 6'b010010 // SPECIAL `define MTLO 6'b010011 // SPECIAL

// 4. Arith Insts
`define ADD 6'b100000 // SPECIAL `define ADDU 6'b100001 // SPECIAL `define SUB 6'b100010 // SPECIAL `define SUBU 6'b100011 // SPECIAL
`define SLT 6'b101010 // SPECIAL `define SLTU 6'b101011 // SPECIAL `define ADDI 6'b001000 `define ADDIU 6'b001001
`define SLTI 6'b001010 `define SLTIU 6'b001011 `define CLZ 6'b100000 // SPECIAL2 `define CLO 6'b100001 // SPECIAL2

`define MUL 6'b000010 // SPECIAL2 `define MULT 6'b011000 // SPECIAL `define MULTU 6'b011001 //SPECIAL // 5. branch insts `define JR 6'b001000 //SPECIAL
//`define JALR 6'b001001 // SPECIAL `define J 6'b000010 //`define JAL 6'b000011 `define BEQ 6'b000100
`define BGTZ 6'b000111 `define BLEZ 6'b000110 `define BNE 6'b000101 `define BLTZ 5'b00000   // REGIMM
//`define BLTZAL 5'b10000 // REGIMM `define BGEZ 5'b00001 // REGIMM //`define BGEZAL 5'b10001 // REGIMM // LOAD and STORE //`define LB 6'b100000
//`define LBU 6'b100100 //`define LH   6'b100001 //`define LHU 6'b100101 `define LW 6'b100011
//`define LWL 6'b100010 //`define LWR  6'b100110 //`define SB 6'b101000 //`define SH 6'b101001
`define SW 6'b101011 //`define SWL  6'b101010 //`define SWR 6'b101110 // ALU OP `define alu_op_nop 8'b00000000
`define alu_op_or 8'b00100101 `define ALU_OP_NOP 8'b00000000 `define ALU_OP_AND 8'b00100100 `define ALU_OP_OR 8'b00100101
`define ALU_OP_XOR 8'b00100110 `define ALU_OP_NOR  8'b00100111 `define ALU_OP_ANDI 8'b01011001 `define ALU_OP_ORI 8'b01011010
`define ALU_OP_XORI 8'b01011011 `define ALU_OP_LUI  8'b01011100 `define ALU_OP_SLL 8'b01111100 `define ALU_OP_SLLV 8'b00000100
`define ALU_OP_SRL 8'b00000010 `define ALU_OP_SRLV  8'b00000110 `define ALU_OP_SRA 8'b00000011 `define ALU_OP_SRAV 8'b00000111

`define ALU_OP_MOVZ 8'b00001010 `define ALU_OP_MOVN 8'b00001011 `define ALU_OP_MFHI 8'b00010000 `define ALU_OP_MTHI 8'b00010001
`define ALU_OP_MFLO 8'b00010010 `define ALU_OP_MTLO 8'b00010011 `define ALU_OP_SLT 8'b00101010 `define ALU_OP_SLTU 8'b00101011
`define ALU_OP_SLTI 8'b01010111 `define ALU_OP_SLTIU  8'b01011000 `define ALU_OP_ADD 8'b00100000 `define ALU_OP_ADDU 8'b00100001
`define ALU_OP_SUB 8'b00100010 `define ALU_OP_SUBU  8'b00100011 `define ALU_OP_ADDI 8'b01010101 `define ALU_OP_ADDIU 8'b01010110
`define ALU_OP_CLZ 8'b10110000 `define ALU_OP_CLO  8'b10110001 `define ALU_OP_MULT 8'b00011000 `define ALU_OP_MULTU 8'b00011001
`define ALU_OP_MUL 8'b10101001 `define ALU_OP_J  8'b01001111 //`define ALU_OP_JAL 8'b01010000 //`define ALU_OP_JALR 8'b00001001
`define ALU_OP_JR 8'b00001000 `define ALU_OP_BEQ  8'b01010001 `define ALU_OP_BGEZ 8'b01000001 //`define ALU_OP_BGEZAL 8'b01001011
`define ALU_OP_BGTZ 8'b01010100 `define ALU_OP_BLEZ  8'b01010011 `define ALU_OP_BLTZ 8'b01000000 //`define ALU_OP_BLTZAL 8'b01001010
`define ALU_OP_BNE 8'b01010010 `define ALU_OP_LW  8'b11100011 `define ALU_OP_SW 8'b11101011 // ALU SEL `define ALU_NOP 3'b000
`define ALU_LOGIC 3'b001 `define ALU_SEL_LOGIC 3'b001 `define ALU_SEL_SHIFT 3'b010 `define ALU_SEL_NOP 3'b000
`define ALU_SEL_MOVE 3'b011 `define ALU_SEL_ARITH 3'b100 `define ALU_SEL_MUL 3'b101 `define ALU_SEL_BRANCH 3'b110
`define ALU_SEL_LOADSTORE 3'b111 //ALU `define ALUOpBus 7:0
`define ALUSelBus 2:0 // DataMem `define DMDataBus 31:0
`define DMAddrBus 31:0 `define DMUnitNum 131071
`define DMunitNumLog2 17 `define ByteWidth 7:0

`include "defines.v" module pc( // ---- input ----- input wire rst, input wire clk, input wire branchEN, input wire[`RegDataBus] branchAddr,	
	input wire[5:0] stall,
	// ---- output ----
	output reg[`InsAddrWidth] pc, output reg insEn ); always@(posedge clk) begin if(rst == `RstEnable) 
		begin
			insEn <= `InsDisable; pc <= `ZeroWord;
		end
		else
		begin
			insEn <= `InsEnable; end end always@(posedge clk) begin if(insEn == `DISABLE)
			pc <= `ZeroWord; else begin if(stall[0] == `DISABLE)
			begin
				if(branchEN == `ENABLE)
					pc <= branchAddr;
				else
				pc <= pc + 4;
			end
		end
	end
endmodule

`include "defines.v" module insMem(insEn, insAddr, inst); // ----- input ------ input wire insEn; input wire[`InsAddrWidth] insAddr;	
	// ----- output -----
	output reg[`InsWidth] inst; reg[`InsWidth] instM[0:`InsMemUnitNum]; initial Begin+ $readmemh("instructions.data",instM); end always@(*) begin if(insEn == `InsDisable) begin
			inst <= `ZeroWord; end else begin inst <= instM[insAddr[`InsMemUnitNumLog2+1:2]];
		end
	end
endmodule

`include "defines.v" module IF_ID( // INPUT input wire rst, input wire clk, input wire[`InsAddrWidth] if_pc,
	input wire[`InsWidth] if_ins, input wire[5:0] stall, //OUTPUT output reg[`InsAddrWidth] id_pc,
	output reg[`InsWidth] id_ins ); always@(posedge clk) begin if(rst == `RstEnable)
		begin
			id_pc <= `ZeroWord; id_ins <= `ZeroWord;
		end
		else
		begin
			if(stall[1] == `ENABLE && stall[2] == `DISABLE)
			begin
				id_pc <= `ZeroWord; id_ins <= `ZeroWord;
			end
			else if(stall[1] == `DISABLE)
			begin
				id_pc <= if_pc;
				id_ins <= if_ins;
			end
		end
	end
endmodule

`include "defines.v" module RegFiles( // INPUT input wire rst, input wire clk, input wire wrn, input wire[`RegAddrBus] wrDataAddr,
	input wire[`RegDataBus] wrData, input wire ren1, input wire[`RegAddrBus] reData1Addr,
	
	input wire ren2,
	input wire[`RegAddrBus] reData2Addr, // OUTPUT output reg[`RegDataBus] reData1,
	output reg[`RegDataBus] reData2 ); // define all registers reg[`RegDataBus] regFiles[0:`RegFilesNum-1]; integer i; // init all registers to be zero initial begin for(i = 0; i < `RegFilesNum; i = i + 1)
			regFiles[i] = `ZeroWord; end // write operation always@(posedge clk) begin if(rst == `RstDisable && wrn == `WriteEnable && wrDataAddr != `RegFilesNumLog2'b0)
		begin
			regFiles[wrDataAddr] <= wrData;
		end	
	end


	// read operation1
	always@(*)
	begin
		if(rst == `ENABLE) reData1 <= `ZeroWord;
		else if(wrn == `ENABLE && wrDataAddr == reData1Addr && ren1 == `ENABLE)
			reData1 <= wrData;
		else if(ren1 == `ENABLE) reData1 <= regFiles[reData1Addr]; else reData1 <= `ZeroWord;
	end
	
	// read operation2
	always@(*)
	begin
		if(rst == `ENABLE) reData2 <= `ZeroWord;
		else if(wrn == `ENABLE && wrDataAddr == reData2Addr && ren2 == `ENABLE)
			reData2 <= wrData;
		else if(ren2 == `ENABLE) reData2 <= regFiles[reData2Addr]; else reData2 <= `ZeroWord;
	end
endmodule

`include "defines.v" module ID_EX( //input input wire clk, input wire rst, input wire[`InsDataBus] id_inst,
	
	input wire[`RegDataBus] id_reg1Data, input wire[`RegDataBus] id_reg2Data,
	
	input wire[`ALUOpBus] id_alu_op, input wire[`ALUSelBus] id_alu_sel,

	input wire[`RegAddrBus] id_wrAddr, input wire id_wrn, input wire id_next_delayslotEn, input wire[5:0] stall, //output output reg[`RegDataBus] ex_reg1Data,
	output reg[`RegDataBus] ex_reg2Data, output reg[`ALUOpBus] ex_alu_op,
	output reg[`ALUSelBus] ex_alu_sel, output reg[`RegAddrBus] ex_wrAddr,
	output reg ex_wrn,

	output reg ex_next_delayslotEn,
	output reg[`InsDataBus] ex_inst ); always@(posedge clk) begin if(rst == `ENABLE)
		begin
			ex_reg1Data <= `ZeroWord; ex_reg2Data <= `ZeroWord;
			ex_alu_sel <= `ALU_NOP; ex_alu_op <= `alu_op_nop;
			ex_wrn <= `DISABLE; ex_wrAddr <= 5'b00000; ex_next_delayslotEn <= `DISABLE;
			ex_inst <= `ZeroWord; end else begin if(stall[2] == `ENABLE && stall[3] == `DISABLE) begin ex_reg1Data <= `ZeroWord;
				ex_reg2Data <= `ZeroWord; ex_alu_sel <= `ALU_NOP;
				ex_alu_op <= `alu_op_nop; ex_wrn <= `DISABLE;
				ex_wrAddr <= 5'b00000;
				ex_next_delayslotEn <= `DISABLE; ex_inst <= `ZeroWord;
			end
			else if(stall[2] == `DISABLE)
			begin
				ex_reg1Data <= id_reg1Data;
				ex_reg2Data <= id_reg2Data;
				ex_alu_op <= id_alu_op;
				ex_alu_sel <= id_alu_sel;
				ex_wrn <= id_wrn;
				ex_wrAddr <= id_wrAddr;
				ex_next_delayslotEn <= id_next_delayslotEn;
				ex_inst <= id_inst;
			end
		end

	end
		
endmodule

`include "defines.v" module EX_MEM( // input input wire clk, input wire rst, input wire wrn_i, input wire[`RegAddrBus] wrAddr_i,
	input wire[`RegDataBus] result_i, input wire wrn_HILO_i, input wire[`RegDataBus] wrData_HI_i,
	input wire[`RegDataBus] wrData_LO_i, input wire[5:0] stall, // mem input wire[`ALUOpBus] alu_op_i,
	input wire[`RegDataBus] mem_addr_i, input wire[`RegDataBus] mem_data_i,

	
	//output
	output reg wrn_o,
	output reg[`RegAddrBus] wrAddr_o, output reg[`RegDataBus] result_o,

	output reg wrn_HILO_o,
	output reg[`RegDataBus] wrData_HI_o, output reg[`RegDataBus] wrData_LO_o,

	//mem
	output reg[`ALUOpBus] alu_op_o, output reg[`RegDataBus] mem_addr_o,
	output reg[`RegDataBus] mem_data_o ); always@(posedge clk) begin if(rst == `ENABLE)
		begin
			wrn_o <= `DISABLE; wrAddr_o <= 5'b00000; result_o <= `ZeroWord;
			wrn_HILO_o <= `DISABLE; wrData_HI_o <= `ZeroWord;
			wrData_LO_o <= `ZeroWord; alu_op_o <= `ALU_OP_NOP;
			mem_addr_o <= `ZeroWord; mem_data_o <= `ZeroWord;
		end
		else
		begin
			if(stall[3] == `ENABLE && stall[4] == `DISABLE)
			begin
				wrn_o <= `DISABLE; wrAddr_o <= 5'b00000; result_o <= `ZeroWord;
				wrn_HILO_o <= `DISABLE; wrData_HI_o <= `ZeroWord;
				wrData_LO_o <= `ZeroWord; alu_op_o <= `ALU_OP_NOP;
				mem_addr_o <= `ZeroWord; mem_data_o <= `ZeroWord;
			end
			else if(stall[3] == `DISABLE)
			begin
				wrn_o <= wrn_i;
				wrAddr_o <= wrAddr_i;
				result_o <= result_i;
				wrn_HILO_o <= wrn_HILO_i;
				wrData_HI_o <= wrData_HI_i;
				wrData_LO_o <= wrData_LO_i;
				alu_op_o <= alu_op_i;
				mem_addr_o <= mem_addr_i;
				mem_data_o <= mem_data_i;
			end
		end
	end

endmodule

`include "defines.v" module dataMem( input wire clk, input wire ce, input wire wrn, // write en input wire[`DMAddrBus] mem_addr,
	input wire[`DMDataBus] mem_data_i, // output output reg[`DMDataBus] mem_data_o
);

	reg[`ByteWidth] DataMEM[0:`DMUnitNum];

	integer i;
	initial
	begin
		for(i = 0; i < `DMUnitNum; i=i+1) begin DataMEM[i] = 8'b0; end end always@(clk) begin if(ce == `ENABLE)
		begin
			if(wrn == `ENABLE) begin { 
    DataMEM[mem_addr],DataMEM[mem_addr+1],DataMEM[mem_addr+2],DataMEM[mem_addr+3]} <= mem_data_i; end end end always@(*) begin if(ce == `DISABLE)
		begin
			mem_data_o <= `ZeroWord;
		end
		else
		begin
			mem_data_o <= { 
   DataMEM[mem_addr],DataMEM[mem_addr+1],DataMEM[mem_addr+2],DataMEM[mem_addr+3]};
		end
	end
endmodule

`include "defines.v" module MEM( //input input wire rst, input wire[`RegDataBus] result_i,
	input wire wrn_i,
	input wire[`RegAddrBus] wrAddr_i, input wire wrn_HILO_i, input wire[`RegDataBus] wrData_HI_i,
	input wire[`RegDataBus] wrData_LO_i, input wire[`ALUOpBus] alu_op_i,
	input wire[`RegDataBus] mem_wrdata_i, input wire[`RegDataBus] mem_addr_i,


	// input from dataMem
	input wire[`RegDataBus] mem_redata_i, //output output reg wrn_o, output reg[`RegDataBus] result_o,
	output reg[`RegAddrBus] wrAddr_o, output reg wrn_HILO_o, output reg[`RegDataBus] wrData_HI_o,
	output reg[`RegDataBus] wrData_LO_o, //output to dataMem output reg mem_wrn, output reg mem_ce, output reg[`RegDataBus] mem_wraddr,
	output reg[`RegDataBus] mem_wrdata ); always@(*) begin if(rst == `ENABLE)
		begin
			wrn_o <= `DISABLE; wrAddr_o <= 5'b00000; result_o <= `ZeroWord;
			wrn_HILO_o <= `DISABLE; wrData_HI_o <= `ZeroWord;
			wrData_LO_o <= `ZeroWord; // about mem mem_wrn <= `DISABLE;
			mem_ce <= `DISABLE; mem_wraddr <= `ZeroWord;
			mem_wrdata <= `ZeroWord; end else begin wrn_o <= wrn_i; wrAddr_o <= wrAddr_i; result_o <= result_i; wrn_HILO_o <= wrn_HILO_i; wrData_HI_o <= wrData_HI_i; wrData_LO_o <= wrData_LO_i; // about mem mem_wrn <= `DISABLE;
			mem_ce <= `DISABLE; mem_wraddr <= `ZeroWord;
			mem_wrdata <= `ZeroWord; case(alu_op_i) `ALU_OP_SW:
					begin
						mem_wrn <= `ENABLE; mem_ce <= `ENABLE;
						mem_wraddr <= mem_addr_i;
						mem_wrdata <= mem_wrdata_i;
					end
				`ALU_OP_LW: begin mem_wrn <= `DISABLE;
						mem_ce <= `ENABLE;
						mem_wraddr <= mem_addr_i;
						result_o <= mem_redata_i;
					end
				default:
					begin
					end
			endcase
		end

	end
endmodule

`include "defines.v" module MEM_WB( //input input wire clk, input wire rst, input wire wrn_i, input wire[`RegAddrBus] wrAddr_i,
	input wire[`RegDataBus] wrData_i, input wire wrn_HILO_i, input wire[`RegDataBus] wrData_HI_i,
	input wire[`RegDataBus] wrData_LO_i, input wire[5:0] stall, //output output reg wrn_o, output reg[`RegAddrBus] wrAddr_o,
	output reg[`RegDataBus] wrData_o, output reg wrn_HILO_o, output reg[`RegDataBus] wrData_HI_o,
	output reg[`RegDataBus] wrData_LO_o ); always@(posedge clk) begin if(rst == `ENABLE)
		begin
			wrn_o <= `DISABLE; wrAddr_o <= 5'b00000; wrData_o <= `ZeroWord;
			wrn_HILO_o <= `DISABLE; wrData_HI_o <= `ZeroWord;
			wrData_LO_o <= `ZeroWord; end else begin if(stall[4] == `ENABLE && stall[5] == `DISABLE) begin wrn_o <= `DISABLE;
				wrAddr_o <= 5'b00000;
				wrData_o <= `ZeroWord; wrn_HILO_o <= `DISABLE;
				wrData_HI_o <= `ZeroWord; wrData_LO_o <= `ZeroWord;
			end
			else if(stall[4] == `DISABLE)
			begin
				wrn_o <= wrn_i;
				wrAddr_o <= wrAddr_i;
				wrData_o <= wrData_i;
				wrn_HILO_o <= wrn_HILO_i;
				wrData_HI_o <= wrData_HI_i;
				wrData_LO_o <= wrData_LO_i;
			end
		end
	end
endmodule

`include "defines.v" module ctrl( input wire rst, input wire id_stall, //input wire ex_stall, output reg[5:0] stall ); always@(*) begin if(rst == `ENABLE)
		begin
			stall <= 6'b000000; end else begin if(id_stall == `ENABLE) begin stall <= 6'b000111;
			end
			else
			begin
				stall <= 6'b000000;
			end
		end
	end

endmodule

`include "defines.v" module min_sopc( // input input wire clk, input wire rst ); wire insEn; wire[`InsDataBus] inst;
	wire[`InsAddrBus] instAddr; wire[`RegDataBus] datamem_mem_redata;
	wire mem_datamem_wrn;
    wire mem_datamem_ce;
    wire[`RegDataBus] mem_datamem_addr; wire[`RegDataBus] mem_datamem_wrdata;

	//OpenMips OpenMips_0
	MIPS_32CPU MIPS32
	(
		// input
		.clk(clk),
		.rst(rst),
		.inst(inst),
		
		// output
		.insAddr_o(instAddr),
		.insEn(insEn),
		.datamem_mem_redata(datamem_mem_redata),
	    .mem_datamem_wrn(mem_datamem_wrn),
        .mem_datamem_ce(mem_datamem_ce),
        .mem_datamem_addr(mem_datamem_addr),
        .mem_datamem_wrdata(mem_datamem_wrdata)
	);

	insMem insMem_0
	(
		//input
		.insAddr(instAddr),
		.insEn(insEn),
		
		// output
		.inst(inst)
	);

	// dataMemory
	dataMem DATAMEM
	(
		.clk(clk),.ce(mem_datamem_ce), .wrn(mem_datamem_wrn),
		.mem_addr(mem_datamem_addr), .mem_data_i(mem_datamem_wrdata),
		.mem_data_o(datamem_mem_redata)
	);
endmodule

`include "defines.v" `timescale 1ns/1ns

module testBench();
	reg CLOCK;
	reg rst;

	initial
	begin
		CLOCK = 1'b0;
		forever #12 CLOCK = ~CLOCK;
	end
	
	initial
	begin
		rst = `ENABLE; #20 rst = `DISABLE;
		#1000 $stop;
	end

	min_sopc min_sopc_0
	(	
		.clk(CLOCK),
		.rst(rst)
	);
endmodule