5.Verilog的阻塞赋值=和非阻塞赋值＜=
赋值 阻塞 Verilog
2023-09-11 14:15:32 时间
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首先看非阻塞赋值<=，参考程序如下：
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2021/12/16 19:34:41
// Design Name:
// Module Name: count
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module count(
input i_clk,
input i_rst,
output reg[9:0]o_count,
output reg o_count1
);
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
o_count <= 10'd0;
o_count1 <= 1'd0;
end
else begin
if(o_count == 10'd