1. 问题描述

        在systemverilog仿真中碰到仿真器报告如下错误：

ncvlog: *E,REFANA (common.sv,4|26): reference argument is illegal inside static task-function declaration.

       出问题的是一个function，其定义如下：

function void DataRead(
    input int     num_data,    
    input string  InputFileName,
    ref logic [7:0]   din_i[128],
    ref logic [7:0]   din_q[128]
);
...funtion body...

2. 解决方案

        一般来说，在module/program中定义的tasks/functions缺省为static类型，根据《IEEE 1800 - 2012》—13.5.2: Pass by reference:

        It shall be illegal to use argument passing by reference for subroutines with a lifetime of static.

       以上这句话是说，对于拥有静态生命时间的子进程（for example, task, function, etc）使用pass-by-reference的方式传递参数是非法的。

        解决方案很简单，就是把出问题的function或者task定义为automatic类型。如下所示：

function automatic void DataRead(
    input int     num_data,    
    input string  InputFileName,
    ref logic [7:0]   din_i[128],
    ref logic [7:0]   din_q[128]
);
...
function body
...

[延申]

1. 为什么不允许对static类型的task/function使用pass-by-reference的方式进行参数传递呢？
2. What is the difference between “static” and “automatic”?
3. What is pass-by-reference, pass-by-value, respectively, and what is the difference between them? Furthermore, what is the benefit of pass-by-reference?

        关于更多关于pass-by-reference的讨论，可以进一步参考下文：

        SystemVerilog: What is and why to use pass-by-reference?