FPGA-3X3矩阵的生成

这里的话我用的是vivado的开发工具

配置shift ram可以实现两行数据的移位，

那再串上一行就可以实现说行数据的移位功能

配置下图：

其他的默认就行，这里我因为是对200*200 *8bit图片数据的进行处理，所以就主要把 位宽和深度定义为自己想要的就好了

module Shift_RAM_3X3(
	//global signals
	input 					clk,						
	input 					rst_n,							
	//Image data prepred to be processd
	input 					per_clken,//Prepared Image data output/capture enable clock
	input 			[7:0]	per_img_Y,//Prepared Image brightness input
	//Image data has been processd
	output					matrix_clken,	//Prepared Image data output/capture enable clock	
	output 	reg 	[7:0]	matrix_p11,						
	output 	reg		[7:0]	matrix_p12,						
	output 	reg		[7:0]	matrix_p13,	//3X3 Matrix output
	output 	reg		[7:0]	matrix_p21,						
	output 	reg		[7:0]	matrix_p22,						
	output 	reg		[7:0]	matrix_p23,						
	output 	reg		[7:0]	matrix_p31,						
	output 	reg		[7:0]	matrix_p32,						
	output 	reg		[7:0]	matrix_p33					
    );
	
//----------------------------------------------
//consume 1clk
wire 	[7:0] 	row1_data;//frame data of the 1th row
wire 	[7:0]	row2_data;//frame data of the 2th row
reg 	[7:0] 	row3_data;//frame data of the 3th row

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		row3_data <= 8'b0;
	else begin
		if(per_clken)
			row3_data <= per_img_Y;
		else
			row3_data <= row3_data;
		end
end

//----------------------------------------------------------
//module of shift ram for row data
wire	shift_clk_en = per_clken;
//Shift_RAM_3X3_8bit1
Shift_RAM_3X3_8bit u1_Shift_RAM_3X3_8bit (
  .D(row3_data),        // input wire [7 : 0] D
  .CLK(shift_clk_en),    // input wire CLK
  .SCLR(~rst_n),  // input wire SCLR
  .Q(row2_data)        // output wire [7 : 0] Q
);
//Shift_RAM_3X3_8bit2
Shift_RAM_3X3_8bit u2_Shift_RAM_3X3_8bit (
  .D(row2_data),        // input wire [7 : 0] D
  .CLK(shift_clk_en),    // input wire CLK
  .SCLR(~rst_n),  // input wire SCLR
  .Q(row1_data)        // output wire [7 : 0] Q
);

//-------------------------------------------
//per_clken delay 3clk	
reg 	[1:0]	per_clken_r;
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		per_clken_r <= 2'b0;
	else 
		per_clken_r <= {per_clken_r[0], per_clken};	 
end

wire 	read_clken = per_clken_r[0];

assign 	matrix_clken = per_clken_r[1];
	 
//---------------------------------------------------------------------
/****************************************
(1)read data from shift_RAM
(2)caulate the sobel
(3)steady data after sobel generate
******************************************/
//wire 	[23:0] 	matrix_row1 = {matrix_p11, matrix_p12,matrix_p13};//just for test
//wire 	[23:0]	matrix_row2 = {matrix_p21, matrix_p22,matrix_p23};
//wire 	[23:0]	matrix_row3 = {matrix_p31, matrix_p32,matrix_p33};
always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		{matrix_p11, matrix_p12, matrix_p13} <= 24'h0;
        {matrix_p21, matrix_p22, matrix_p23} <= 24'h0;
        {matrix_p31, matrix_p32, matrix_p33} <= 24'h0;
	end
//	else if(read_frame_href)begin
	else if(read_clken)begin//shift_RAM data read clock enbale 
			{matrix_p11, matrix_p12, matrix_p13} <= {matrix_p12, matrix_p13, row1_data};//1th shift input
			{matrix_p21, matrix_p22, matrix_p23} <= {matrix_p22, matrix_p23, row2_data};//2th shift input 
			{matrix_p31, matrix_p32, matrix_p33} <= {matrix_p32, matrix_p33, row3_data};//3th shift input 
		end
	else begin
		{matrix_p11, matrix_p12, matrix_p13} <= {matrix_p11, matrix_p12, matrix_p13};
		{matrix_p21, matrix_p22, matrix_p23} <= {matrix_p21, matrix_p22, matrix_p23};
		{matrix_p31, matrix_p32, matrix_p33} <= {matrix_p31, matrix_p32, matrix_p33};
			end
//	end
/* 	else begin
		{matrix_p11, matrix_p12, matrix_p13} <= 24'h0;
        {matrix_p21, matrix_p22, matrix_p23} <= 24'h0;
        {matrix_p31, matrix_p32, matrix_p33} <= 24'h0;
		end */
end	
	
endmodule