题目

设置一个计数器，从0开始计数，一直计数到3，然后回到0，根据计数器的值，来决定乘以多少，再设置一个valid信号，标志输入数据d有效，首先，复位时valid应该为1，其次，当计数器的值为3的时候，valid也应该为1，当valid为1时，我们还需要寄存输入数据d,即d_r<=d,同时拉高input_grant一个周期。

代码

module top(
    input logic clk,
    input logic rst,
    input logic [7:0] d,
    output logic [15:0] out,
    output logic input_grant
);
logic [7:0] d_r;
logic valid;
logic [1:0] cnt;
//valid
always_ff@(posedge clk,posedge rst)
if(rst)
    valid<=1;
else if(cnt==2)
    valid<=1;
else
    valid<=0;
//cnt
always_ff@(posedge clk,posedge rst)
if(rst)
    cnt<=0;
else if(valid)
    cnt<=0;
else if(cnt==4-1)
    cnt<=0;
else
    cnt<=cnt+1;
//d_r
always_ff@(posedge clk)
if(valid)    
    d_r<=d;
//out
always_comb 
begin
if(rst)
    out=0;
else
begin
    case(cnt)
        2'd0:out=d_r;
        2'd1:out=(d_r<<1)+d_r;                //x3
        2'd2:out=(d_r<<2)+(d_r<<1)+d_r;       //x7
        2'd3:out=d_r<<3;                      //x8
    endcase    
end
end
//input_grant
always_ff@(posedge clk,posedge rst)
if(rst)
    input_grant<=0;
else if(valid)
    input_grant<=1;
else 
    input_grant<=0;

endmodule

测试平台

module test;
logic clk;
logic rst;
logic [7:0] d;
logic [15:0] out;
logic input_grant;
//
initial begin
    clk=0;
    forever begin
        #5 clk=~clk;
    end
end
//
initial begin
    rst=1;
    #100
    rst=0;
end
//
always_ff@(posedge clk,posedge rst)
if(rst)
    d<=0;
else 
    d<=$urandom%256;
//
initial
begin
   $fsdbDumpfile("./top.fsdb");
   $fsdbDumpvars(0);
end
//
initial
begin
   #10000
   $finish;
end
//
top U(.*);

endmodule

仿真结果