verilog 多路选择器四选一

`timescale 1ns/1ns

module  mux4to1( input [1:0] d0 ,d1 ,d2,d3,sel,
 
           output [1:0] mux_out
                  );
    reg [1:0] mux_out;
    always @(*)begin 
        case (sel)
             2'b00 :mux_out=d0;
             
             2'b01 :mux_out=d1;
             2'b10 :mux_out=d2;
             2'b11 :mux_out=d3;
             default :mux_out=d0;
        endcase 

    end 

    endmodule






`timescale 1ns/1ns

module test ;
    reg [1:0]    sel ;
    wire [1:0]   sout ;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0,test);
         sel     = 0 ;
        #10 sel   = 3 ;
        #20 ;
        #10 sel   = 1 ;
        #20 ;
        #10 sel   = 0 ;
        #20 ;
        #10 sel   = 2 ;
    end

    mux4to1 u_mux4to1 (
       
        .d0     (2'b00),        //path0 are assigned to 0
        .d1     (2'b01),        //path1 are assigned to 1
        .d2     (2'b10),        //path2 are assigned to 2
        .d3     (2'b11),  
         .sel    (sel),      //path3 are assigned to 3
        .mux_out   (sout));

   //finish the simulation
    always begin
        #100;
        if ($time >= 1000) $finish ;
    end

 
endmodule